1. Field of the Invention
The present invention relates to a semiconductor device and fabrication method thereof, and in particular relates to a deep trench contact structure and fabrication method thereof.
2. Description of the Related Art
For present semiconductor techniques, an operating single-chip system has been achieved by integrating controllers, memory devices, low-operation-voltage circuits and high-operation-voltage power devices, into a chip. Research development of power devices, such as vertical double diffused metal oxide semiconductor (VDMOS), insulated gate bipolar transistors (IGBT), lateral double diffused metal oxide semiconductor (LDMOS), or etc., has focused on increasing efficiency to decrease energy loss of the devices. Meanwhile, high voltage transistors and the low voltage CMOS circuits are integrated into a chip, thus isolation structures are formed for isolating adjacent devices.
FIG. 1 shows a cross-section view of a conventional high-voltage device as disclosed in U.S. Pat. No. 7,242,070 B2. An N-type epitaxy layer 40 is formed on a P-type semiconductor substrate 10. P+-type isolation structures 50, defining active regions for high-voltage devices of VDNMOS and bipolar transistor, are formed in the N-type epitaxy layer 40. Field oxide (FOX) layers 18 are formed on the N-type epitaxy layer 40 for isolating device structures in the active region of the high-voltage device. The VDNMOS comprises a P-type body 36 in the N-type epitaxy layer 40, an N-type doped region 32 and P-type doped region 34 in the P-type body 36, and a gate structure 30 on the N-type epitaxy layer 40. The bipolar transistor comprises a P-type body 36′ in the N-type epitaxy layer 40, and an N-type doped region 32′ and P-type doped region 34′ in the P-type body 36′. N+-type trench contacts 60 and 60′ are formed in the N-type epitaxy layers 40 in the active regions of the high-voltage devices. The N+-type trench contacts 60 and 60′ pass through the N-type epitaxy layers 40, and are partially embedded in N-type buried layers 2 and 2′ between the N-type epitaxy layer 40 and P-type semiconductor substrate 10. The N+-type trench contacts 60 and 60′ are electrically connected to contact plugs 19 in an inter-layer dielectric layer 16 and metal layers 21 on the contact plugs 19.
The N+-type trench contacts 60 and 60′ are usually formed by doping an N-type dopant with a high dosage and a high energy and annealing with a high thermal budget. The N+-type trench contacts 60 and 60′ of high-concentration dopant would be easily polluted by an out gassing generated in the annealing process and contaminants in the process environment, resulting in low device efficiency. For obtaining a proper breakdown voltage and adapting in process feasibility, the N+-type trench contacts 60 and 60′ have to be far away from the P+-type isolation structures 50. However, the number of the devices can be constructed in a single wafer is thus limited.
FIG. 2 is a cross-section view of one other conventional high-voltage device. A deep trench isolation structure 70 formed with a dielectric material replaces the P+-type isolation structure 50 of FIG. 1. The deep trench isolation structure 70 can be used for improving the area of the active region of the high-voltage device. However, the deep trench isolation structure 70 must be much deeper than N-type epitaxy layers 40 so as to prevent noise caused from the high-voltage condition. It is not easy to fabricate the deep trench isolation structure 70 to high degree of depth. In addition, controlling the aspect ratio of the deep trench isolation structure 70 is also a challenge. Therefore, the improvement for the operating voltage of the high-voltage device is limited.
An improved semiconductor device and fabrication method thereof ameliorating the disadvantages of the conventional technology is desirable.